1. Technical Field
Embodiments of the present invention relate to a duty cycle correcting circuit and a duty cycle correcting method, and more particularly, to a digital-type duty cycle correcting circuit and a duty cycle correcting method that may be capable of generating a clock having an improved duty ratio quality.
2. Related Art
In general, a DLL (Delay Locked Loop) circuit is included in a semiconductor integrated circuit. The DLL circuit makes a phase of an internal clock earlier than a phase of an external clock by a predetermined time to compensate for a delay time due to internal delay elements until the internal clock can synchronize with the data. Therefore, output data is not delayed more than the external clock. The internal clock is used to control a data output buffer.
In the internal clock that is generated by the DLL circuit, it is difficult to accurately make a duty ratio 50:50. Therefore, the DLL circuit includes a duty cycle correcting circuit to adjust the duty ratio of the internal clock. Examples of the duty cycle correcting circuit include an analog-type duty cycle correcting circuit and a digital-type duty cycle correcting circuit. In general, the analog-type duty cycle correcting circuit is superior to the digital-type duty cycle correcting circuit, and the analog-type duty cycle correcting circuit generates a clock having better duty ratio quality. However, the analog-typed duty cycle correcting circuit has disadvantages in that it takes a large amount of time to perform a duty cycle correcting operation, occupies a large area and consumes a large amount of current. Meanwhile, the digital-type duty cycle correcting circuit has advantages in that it has a relatively short operation time, occupies a small area, and consumes a small amount of current, but has a disadvantage in that it has a clock duty ratio correcting function inferior to the analog-type duty ratio correcting circuit.
As a semiconductor integrated circuit operates at a high speed, is highly integrated, and consumes low power, it is preferable to implement the digital-type duty cycle correcting circuit that generates a clock having an improved duty ratio quality. However, there exist technical limits in implementing the digital-type duty cycle correcting circuit having the more improved operation ability.